(1) Field of the Invention
The invention relates to an input signal conditioning circuit, and more particularly, to a minimum pulse width detection and regeneration circuit.
(2) Description of the Prior Art
Electronic circuits frequently encounter the problem of small pulse width signals, or glitches. Glitches are often caused at the interface of various integrated circuit components in a system, especially where various components are not synchronized (asynchronous) with a common system clock. Glitches can also occur in synchronized systems due to excessive fan-out, loading, or noise.
Referring now FIG. 1, a common prior art signal timing diagram is shown. In this diagram, the system clock CLK is represented by a constant periodic signal. An address bus for a memory device ADDR is represented as a sequence of bus states and transitions. To access a location in the memory device, such as a DRAM, for either a read or a write of data, the micro-controller must select the location by forcing the address bus to the desired memory address. As a matter of specification, this address setting must be performed such that a stable address proceeds the clock edge, in this case a falling edge, by a minimum setup time tS. In addition, the address must be stable for a minimum hold time, tH, after the falling edge CLK. The specification of these setup and hold values is used to eliminate internal glitch signals within the memory device and may be specified for addresses, data, and command pins.
The use of setup and hold specifications may not always prevent the creation of glitches due to the above-mentioned problems of fan-out, loading, noise, as well as other problems. Sometimes the design of the system creates asynchronous interfaces that are difficult to design around. Referring now to FIG. 2, a prior art example of the creation of an internal glitch is shown. In this example, an AND gate 10 is used to logically combine the signals A and B to create the signal C. The timing diagram shows a problematic case where the transitions of A and B occur in close proximity. This causes a momentary assertion 14 of C. This glitch 14 may not be intended and, indeed, may not show up during simulation verification due to unaccounted for parasitics or due to device variation. However, the propagation of this glitch 14 may have serious consequences for circuit operation.
Once a short duration pulse or glitch has been introduced into the digital circuit, it can be removed using a filtering circuit. Referring now to FIG. 3, a filtering circuit of the prior art is shown. In this circuit, positive glitches, where the IN signal has a momentary pulse from a low level to a high level and then back to a low level, can be filtered away. Only positive glitches on IN having a length of greater than the propagation delay of the delay element 28 are passed through the NAND gate 20 and the inverter 24 to the output OUT. The key problem with the prior art filter approach is that a new glitch may be generated by the filter itself if the input pulse has a length of slightly greater than the delay element propagation. Therefore, the prior art approach is insufficient to solve the problem.
Referring now to FIG. 4, a glitch lengthening circuit is shown. This circuit uses a delay element 36 and a NOR gate 32 to cause the length of a positive pulse on the input IN to be lengthened by the amount of time introduced by the delay circuit. While this approach may work for some cases, the drawback is that a large, but destructive, glitch may be generated from a small or non-destructive glitch.
Several prior art inventions describe input signal processing and glitch removing circuits. U.S. Pat. No. 6,075,751 to Tedrow describes a circuit to detect and synchronize input signals. The circuit comprises a filter and a pulse generator. U.S. Pat. No. 5,113,098 to Teymouri discloses a glitch removing circuit for a transmission link. A hysteresis input buffer and a filter circuit are used. U.S. Pat. No. 5,563,532 to Wu et al teaches a glitch filter comprising a Schmitt trigger and a series of three active filters.
A principal object of the present invention is to provide an effective and very manufacturable minimum pulse width detection and regeneration circuit.
A further object of the present invention is to provide a circuit that can detect if a signal pulse width is in the range between a minimum width and a maximum width.
A still further object of the present invention is to provide a circuit that can pass the signal pulse if it exceeds the minimum width and filter out the signal pulse if it is less than the minimum width.
Another still further object of the present invention is to provide a circuit that can extend the pulse width of the signal pulse to the maximum width if the input pulse is in the range.
In accordance with the objects of this invention, a minimum pulse width detection and regeneration circuit is achieved. The circuit comprises, first, a pulse width detector capable of detecting if an input signal pulse is within a range between a minimum width and a maximum width. Second, a pulse width extender is capable of extending the input signal pulse width to the maximum width if the input signal pulse is in the range. Finally, a glitch filter is capable of filtering out the input signal pulse if the input signal pulse is less than the minimum width.
Also in accordance with the objects of this invention, a minimum pulse width detection and regeneration circuit is achieved. The circuit comprises, first, a latch having set, reset, and output. The set is coupled to an input signal. Second, a glitch filter has an input and an output. The input is coupled to the latch output. The input is delayed to create a delayed input. Finally, a delay element has an input and an output. The delay element input is coupled to the glitch filter delayed input. The delay element output is coupled to the latch reset.